FIG. 1 shows a digital data link comprising a transmitter and a receiver being clocked by respective phase-locked-loop circuits (PLLs). The transmitter transmits data at a given transmit clock rate and the receiver clocks the data in using its local clock. However the two clock frequencies may not be exactly the same. Both crystals 11 will have a frequency error (typically up to 500 ppm) and there may also be an error in the frequency generated by the PLL at either end. For example, both PLLs may be fractional-N PLLs (known circuits, able to synthesise output signals having frequencies which are non-integer multiples of the reference frequency) provided with the same input frequency (i.e. the same reference signal) but having subtly different divider ratios. The output frequencies of the PLLs may both meet a specified minimum and maximum frequency range, although they are in fact slightly different. Even a few ppm difference on, say, a 12 MHz data stream could give missing bits several times a second, which would be completely unacceptable for both digital audio data or indeed more general data streams. So, in many systems it is desirable to have a capability to synchronise a locally generated clock and a remotely generated clock. For example it is desirable to generate a clean clock locally and retime the incoming data to this clock prior to a digital-to-analogue converter to avoid clock-jitter induced noise and distortion. The local clock and the incoming data clock would need synchronising to avoid data loss. Synchronised clocks also prevent buffer under/over run in data receivers.
The clocking information can either be sent from transmitter to receiver as a separate signal channel, or embedded in the data stream. However, even in the first case, the clock may have been corrupted by the time it reaches the receiver. Cross-talk onto the clock channel from data channels, extraneous noise and interference, and jitter added by the transmit buffer compounded by frequency attenuation from cables or other forms of distortion in a more general communication channel can all degrade the spectral purity of the received clock. In the absence, for economy or channel bandwidth reasons, of a separate clock channel, the received clock must be derived from the received data: this generally also adds extra received clock jitter from both data-dependent sources such as inter-symbol interference and from non-idealities in the clock extraction circuitry In many applications, such as high-resolution audio data converters, the spectral purity of the clock can be limiting factor for THD (total harmonic distortion) and SNR (signal-to-noise ratio). To this end the received clock usually needs to have the jitter attenuated to improve performance of the receiving device.
There is a subtle distinction between the remote clock, i.e. the clock as observable at the transmitter, and the received clock, i.e. the clock observable at the receiver. The long-term average frequency of the two is equal, so if a local clock is synchronised to the received clock, it is also synchronised to the remote clock. However, it is the received clock, with additional short-term jitter as described above, which is actually used in any signal processing at the receiver, so the receiver must also attenuate this undesirable jitter.
One method of solving the problem of data loss due to remote and local clocks slipping past each other involves the use of an elastic buffer. An elastic buffer is a buffer that is used to hold enough data to ensure that when the clocks beat no data is lost. However the size of elastic buffer can be large for extremely jittery clocks and one buffer is required for each channel of data. For multiple channel systems the size of the elastic buffer can become the dominating issue
To address the problem of minimising the jitter on the local clock, traditionally clock synchronisers have been implemented by using analogue phase locked loops, with large off-chip components necessary to provide low-frequency time-constants to filter out the jitter on the reference clock. In practice, two PLLs may be needed, one with wide enough bandwidth to track the incoming clock and recover the data and another PLL with low bandwidth used to reduce the amount of jitter on the recovered clock.
Off-chip components increase the cost and physical size of the design. They can also degrade the performance unless great care is exercised. “Ground bounce” or transient differences between the ground off- and on-chip due to wideband ground return currents flowing through the chip ground connections are inevitable and can possibly even introduce more jitter than the loop filter is attenuating from the remote clock.
There is thus a need for a system that can generate a clock that is the same frequency as an incoming data clock (i.e. a received clock), but with substantially less jitter than that of the data clock as received. Preferably this clock synchroniser should be low-cost, and require a minimum of external components. Also, to reduce the amount of hardware in multi-channel systems it is generally preferable to synchronise to one clock common to all channels rather than to the data on each channel.